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| SSM3310GH,J P-channel Enhancement-mode Power MOSFET 2.5V low gate drive capability Simple drive requirement Fast switching Pb-free; RoHS compliant. D BV DSS R DS(ON) ID -20V 150m -10A G S DESCRIPTION The SSM3310GH is in a TO-252 package, which is widely used for commercial and industrial surface mount applications, and is well suited for use in low voltage battery applications. The through-hole version, the SSM3310GJ in TO-251, is available for low-footprint vertical mounting. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. G D S GD S TO-252 (H) TO-251 (J) ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID @ TC=25C ID @ TC=100C IDM PD @ TC=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 Rating -20 12 -10 -6.2 -24 25 0.2 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range THERMAL DATA Symbol Rthj-c Rthj-a Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 5 110 Unit C/W C/W 2/16/2005 Rev.2.1 www.SiliconStandard.com 1 of 7 SSM3310GH,J Electrical Characteristics @ Tj=25C (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=-250uA Min. Typ. Max. Units -20 -0.5 -0.1 - V V/C BV DSS/Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=-1mA Static Drain-Source On-Resistance VGS=-4.5V, ID=-2.8A VGS=-2.5V, ID=-2.0A 4.4 6 1.5 0.6 25 60 70 60 300 180 60 150 m 250 m -1 -25 V S uA uA nC nC nC ns ns ns ns pF pF pF VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=150 C) o o VDS=VGS, ID=-250uA VDS=-5V, ID=-2.8A VDS=-20V, VGS=0V VDS=-16V, VGS=0V VGS= 12V ID=-2.8A VDS=-6V VGS=-5V VDS=-6V ID=-1A RG=6, VGS=-5V RD=6 VGS=0V VDS=-6V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 100 nA Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol IS ISM VSD Parameter Continuous Source Current ( Body Diode ) Test Conditions VD=VG=0V , VS=-1.2V 1 Min. Typ. Max. Units -10 -24 -1.2 A A V Pulsed Source Current ( Body Diode ) Forward On Voltage 2 Tj=25C, IS=-10A, VGS=0V Notes: 1.Pulse width limited by safe operating area. 2.Pulse width <300us , duty cycle <2%. 2/16/2005 Rev.2.1 www.SiliconStandard.com 2 of 7 SSM3310GH,J 24 20 -4.5V T C =25 C o T C =150 o C -4.5V 18 -4.0V 15 -4.0V -ID , Drain Current (A) -ID , Drain Current (A) -3.5V 12 -3.5V 10 -3.0V -3.0V -2.5V 5 6 -2.5V V GS = -2.0V V GS = -2.0V 0 0.0 2.5 5.0 7.5 10.0 0 0 2 4 6 8 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 800 1.8 I D = -2.8A T C =25C 600 I D = -2.8A V GS = -4.5V 1.5 400 Normalized R DS(ON) 0 2 4 6 8 10 RDS(ON) (m ) 1.2 200 0.9 0 0.6 -50 0 50 100 150 -V GS (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 2/16/2005 Rev.2.1 www.SiliconStandard.com 3 of 7 SSM3310GH,J 10 30 25 8 -ID , Drain Current (A) 20 6 PD (W) 4 2 0 25 50 75 100 125 150 15 10 5 0 0 50 100 150 T c , Case Temperature ( o C) T c , Case Temperature ( o C) Fig 5. Maximum Drain Current vs. Case Temperature Fig 6. Typical Power Dissipation 100 1 Duty Factor = 0.5 Normalized Thermal Response (R thjc) 0.2 100us -ID (A) 0.1 0.1 0.05 10 1ms 0.02 PDM Single Pulse t 0.01 T 10ms T C =25 C Single Pulse 100ms 1 1 10 100 Duty Factor = t/T Peak T j = PDM x Rthjc + TC 0.01 0.00001 0.0001 0.001 0.01 0.1 1 -V DS (V) t , Pulse Width (s) Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance 2/16/2005 Rev.2.1 www.SiliconStandard.com 4 of 7 SSM3310GH,J f=1.0MHz 5 1000 I D =-2.8A V DS =-6V 4 Ciss -VGS , Gate to Source Voltage (V) 3 Coss C (pF) 100 2 Crss 1 0 0 2 4 6 8 10 1 3 5 7 9 11 13 Q G , Total Gate Charge (nC) -V DS (V) Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics 10 1.5 T j =150 o C T j =25 o C 1 1 -VGS(th) (V) 0.5 0 0.3 0.5 0.7 0.9 1.1 1.3 1.5 -50 0 50 o -IS(A) 0 100 150 -V SD (V) T j , Junction Temperature ( C) Fig 11. Forward Characteristic of Reverse Diode Fig 12. Gate Threshold Voltage vs. Junction Temperature 2/16/2005 Rev.2.1 www.SiliconStandard.com 5 of 7 SSM3310GH,J VDS RD 90% D VDS TO THE OSCILLOSCOPE 0.3 x RATED VDS RG G 10% S -5 V VGS VGS td(on) tr td(off) tf Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform VG VDS TO THE OSCILLOSCOPE 0.3 x RATED VDS G S -1~-3mA I G QG D -5V QGS QGD VGS ID Charge Q Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform 2/16/2005 Rev.2.1 www.SiliconStandard.com 6 of 7 SSM3310GH,J Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 2/16/2005 Rev.2.1 www.SiliconStandard.com 7 of 7 |
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